Espressif Systems /ESP32-P4 /SPI0 /SPI_MEM_DOUT_MODE

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Interpret as SPI_MEM_DOUT_MODE

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPI_MEM_DOUT0_MODE)SPI_MEM_DOUT0_MODE 0 (SPI_MEM_DOUT1_MODE)SPI_MEM_DOUT1_MODE 0 (SPI_MEM_DOUT2_MODE)SPI_MEM_DOUT2_MODE 0 (SPI_MEM_DOUT3_MODE)SPI_MEM_DOUT3_MODE 0 (SPI_MEM_DOUT4_MODE)SPI_MEM_DOUT4_MODE 0 (SPI_MEM_DOUT5_MODE)SPI_MEM_DOUT5_MODE 0 (SPI_MEM_DOUT6_MODE)SPI_MEM_DOUT6_MODE 0 (SPI_MEM_DOUT7_MODE)SPI_MEM_DOUT7_MODE 0 (SPI_MEM_DOUTS_MODE)SPI_MEM_DOUTS_MODE

Description

MSPI flash output timing adjustment control register

Fields

SPI_MEM_DOUT0_MODE

the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge

SPI_MEM_DOUT1_MODE

the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge

SPI_MEM_DOUT2_MODE

the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge

SPI_MEM_DOUT3_MODE

the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge

SPI_MEM_DOUT4_MODE

the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk

SPI_MEM_DOUT5_MODE

the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk

SPI_MEM_DOUT6_MODE

the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk

SPI_MEM_DOUT7_MODE

the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk

SPI_MEM_DOUTS_MODE

the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk

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